[SV]Verilog系统任务及应用实例 ---- 時序检查任务及应用案例（Timing check tasks and example）
引言：時序檢查（Timing Check）是數字驗證中的主要任務之一，Verilog系统Timing Check任务在指定块中使用，以执行常见的定时检查。本文將歸納常用的Timing Check任務。
一、Verilog Timing Check Task 1.1、Timing check task list| No. | Task原型 | 注釋 |
| 1 | $setup(data_event, reference_event, limit [ , notifier ] ); | checks setup time |
| 2 | $hold(reference_event, data_event, limit [ , notifier ] ); | |
| 3 | $setuphold(reference_event, data_event, setup_limit, hold_limit [ , notifier ]); | |
| 4 | $period(reference_event, limit [ , notifier ] ); | |
| 5 | $width(reference_event, limit [ , treshold [ , notifier ]] ); | |
| 6 | $skew(reference_event, data_event, limit [ , notifier ] ); | |
| 7 | $recovery(reference_event, data_event, limit [ , notifier ] ); | |
| 8 | $nochange(reference_event, data_event, start_edge_offset, end_edge_offset [ , notifier ] ); | |
| 9 | $removal(reference_event, data_event, limit [ , notifier ] | |
| 10 | $recrem(control_event, data_event, recovery_limit, removal_limit [ , notifier ] | |
| 11 | $timeskew(reference_event, data_event, limit [ , notifier ] [ , event_based_flag ] [ , remain_active_flag ]; | |
| 12 | $fullskew(reference_event, data_event, limit [ , notifier ] [ , event_based_flag ] [ , remain_active_flag ]; |
| 參數 | 含義 | 類型 |
|---|---|---|
| reference_event | The transition at a control signal that establishes the reference time for tracking timing violations on the data_event | Module input or inout that is scalar or vector net |
| data_event | The signal change that initiates the timing check and is monitored for violations. | Module input or inout that is scalar or vector net |
| limit | A time limit used to detect timing violations on the data_event | Constant expression or specparam |
| threshold | The largest pulse width that is ignored by the timing check $width | Constant expression or specparam |
| setup_limit | A time limit used to detect timing violations on the data_event for $setup | Constant expression or specparam |
| hold_limit | A time limit used to detect timing violations on the data_event for $hold | Constant expression or specparam |
| notifier | An optional argument that "notifies" the simulator when a timing violation occurs | Register |
| Task | Description | Comment |
|---|---|---|
| $setup | checks setup time,When modeling synchronous circuits, flip-flops need time to force a correct value. Data cannot change within the setup time because flip-flops cannot detect the new value. If data changes within a given time limit,$setupreports a timing violation. |
The formula to report a timing violation is as shown: (time of reference event) - (time of data event) < limit If a data event and reference event occur at the same time there is no violation. The $setupfirst checks timing data then records a new data value. |
| $hold |
will report a timing violation if the following formula is true: (time of data event) - (time of reference event) < limit |
$hold simply checks that data is stable in the specified interval of time after the edge of the clock. In flip-flops, data should remain stable for a given time after the active edge of the clock to allow for propagation of data. Also, a violation will be reported if the data event and the reference event occur at the same time. |
| $recovery |
responds when the following formula is true: (time of data event) - (time of reference event) < limit |
The 'reference_event' must be an edge-triggered event: posedge or negedge. A timing violation occurs if the time interval between an edge-triggered reference event and a data event exceeds the 'limit'. If a reference event and data event occur at the same time, a timing violation is reported. If a 'reference_event' argument is specified without edge specification, an error is reported. |
| $skew | (time of data event) - (time of reference event) > limit |
$skewcan be used to check synchronicity of clocks inside a circuit. If different clocks are used in a design and are synchronized,$skewwill report a timing violation when the active edge of one of them occurs outside the time limit allowed for the other clock to occur. When the data event and the reference event occur at the same time,$skew will not report a timing violation. |
| $setuphold |
checks setup and hold timing violations. This task combines the functionality of $setup and $hold in one task. The following formula has to be applied: setup_limit + hold_limit > 0 |
|
| $period |
The $period reports a timing violation when the following formula comes true: (time of data event) - (time of reference event) < limit |
checks that a period of signal is sufficiently long. The reference_event has to be an edge specification. The data_event is not specified directly and by default, is the same as a reference_event. |
| $nochange | checks if the data signal is stable in an interval of start_edge_offset and end_edge_offset. If the signal has changed, a timing violation is reported. The reference_event argument can be posedge or negedge but the edge control specifiers are disallowed. | |
module setup_exp (data1, data2, q);
input data1, data2;
output q;
and(q, data1, data2);
specify
specparam tsetup = 7, delay = 10 ;
(data1 => q) = 10 ;
$setup(data1, posedgedata2, tsetup);
endspecify
endmodule
2.2、$skew() 使用案例
module skew_exp(clk1, clk2, q);
input clk1, clk2;
output q;
specify
specparam tskew = 7;
$skew(posedge clk1, posedge clk2, tskew);
endspecify
endmodule
2.3、$hold() 使用案例
module hold_exp(data1, data2, q);
input data1, data2;
output q;
and(q, data1, data2);
specify
specparam thold = 7, delay = 10 ;
(data1 => q) = 10 ;
$hold(posedge data2, data1, thold);
endspecify
endmodule
2.4、$recovery() 使用案例
module recovery_exp(in1, out1);
input in1;
output out1;
assign out1 = in1? 1'b1 : 1'bz;
specify
specparam trecovery = 10;
$recovery(posedgein1, out1, trecovery);
endspecify
endmodule
2.5、$setuphold()使用案例
module setuphold_exp(data1, data2, q);
input data1, data2;
output q;
and(q, data1, data2);
specify
specparam tsetup = 7,
thold = 7,
delay = 10 ;
(data1 => q) = 10 ;
$setuphold(posedge data2, data1, tsetup, thold);
endspecify
endmodule
2.6、$width()使用案例
module width_exp (data1, data2, q);
input data1, data2;
output q;
and(q, data1, data2);
specify
specparam twidth = 10,
delay = 10 ;
(data2 => q) = 10 ;
$width(posedge data2, twidth);
endspecify
endmodule
2.7、$period()使用案例
module period_exp(clk, q);
input clk;
output q;
buf(q, clk);
specify
specparam tperiod = 100 ;
$period(posedgeclk, tperiod);
endspecify
endmodule
2.8、nochange()使用案例
module nochange_exp(data1, data2, q);
input data1, data2;
output q;
and(q, data1, data2);
specify
specparam tstart = -5,
tend = 5 ;
$nochange(posedge data2, data1, tstart, tend);
endspecify
endmodule
三、參考資料
3.1、Link
3.2、Link
作者：gsithxy
